The present invention relates to a semiconductor memory device and to an amplifier which can be used with such a device.
Generally, a semiconductor memory device is provided with memory elements formed of insulated gate field effect transistors (MOS FETs). A semiconductor memory can either be a dynamic memory device or a static memory device. The dynamic memory device is suitable for high density integrated circuit fabrication, while the static memory device is suitable as a high speed memory device because of less restriction on timing for its operation.
From a viewpoint of the semiconductor manufacturing technology, MOS memory is classified into metal gate MOS memory devices formed of metal gate MOS transistors using metal gate electrodes with extremely small sheet resistance, and silicon gate MOS memory devices formed of silicon gate MOS FETs having gates made of polysilicon with a higher sheet resistance than that of the metal. The metal gate MOS memory does not use the polysilicon layer. For this reason, it needs fewer steps to manufacture, but it needs a relatively large area for wiring. On the other hand, the silicon gate MOS memory requires an additional step to form the polysilicon layer, resulting in complexity of the manufacturing process.
FIG. 1 shows a semiconductor memory device formed of silicon gate MOS memory elements. The semiconductor memory device includes a plurality of MOS memory cells MC-11 to MC-MN arranged in a matrix fashion, paired data lines D0-1 and D1-1, D0-2 and D1-2, . . . , and D0-N and D1-N, which are commonly connected to input and output terminals of the memory cells on the same column, and word lines W1 to WM each transferring an address signal for access to specified memory cells on the same row. Those word lines W1 to WM are connected to a row decoder 2 which receives a row address from an address signal generator (not shown) to selectively energize the word lines. The data lines D0-l to D0-N and D1-1 to D1-N are connected to a column decoder/sense amplifier 4 which responds to a column designating signal from the address signal generator to selectively energize the data lines and supply the data read out from a desired memory cell to a data processor (not shown), by way of an I/O unit 6.
With the semiconductor memory device thus constructed as shown in FIG. 1, to execute a read operation, the row decoder 2 and the column decoder 4 respond to an address signal from an address signal generator (not shown) to selectively energize one of the word lines W1 to WM and one of pairs of the data lines D0-1 to D0-N and D1-1 to D1-N. Upon energization, the memory cells coupled with the word lines energized correspondingly produce the stored data. Of those data, only the data transferred to the pair of data lines selected by the column decoder/sense amplifier 4 is amplified by the sense amplifier 4 and then is transmitted to an I/O unit 6.
A data read time, from which is the instant that the row and column address signals are respectively supplied to the row decoder 2 and the column decoder 4 until the instant that the data read out of a desired memory cell is transferred to the I/O unit 6, depends on the setup time of the row decoder 2, the transfer time of the row address signal on the word line, the transfer time of the data on the data line, and the transfer time of the data from the sense amplifier 4 to the I/O unit 6. It should be noted here that the transfer time of the row address signal on the word line generally has the greatest influence upon the data read time, since the word line is formed of the polysilicon layer with a high sheet resistance, as previously stated. As a consequence, in constructing a high speed memory device, it is essential to minimize the transfer time of the row address signal on the word line thereby to reduce the over-all operation delay time.
Certain measures, such as one shown in FIG. 2, have successfully reduced the read operation delay to some extent. However, along with the recent demand on the speed-up of the memory speed, it is required to reduce the time delay in the readout operation even further.
Accordingly, an object of this invention is to provide a positive feedback amplifier for use with a semiconductor device to shorten the access time to memory cells.